The present invention relates to the field of instruction-controlled digital computers and specifically, to the processing of condition-code-setting instructions and branch-on-condition instructions, such as defined, for example, by OS/370 architecture.
Branch-on-condition instructions are an important part of the data processing system. The manner in which these instructions are processed is an important factor in the cost and performance of the system because such instructions are statistically common instructions in programs.
When branch instructions are processed, they require the interrogation of a condition code (CC), which is set by a previous condition-code-setting instruction, to determine which of two instruction streams will be thereafter followed. In a pipelined environment, the branch-on-condition instruction will start execution before the completion of execution of the condition-code-setting instruction. The condition-code-setting instruction should determine the condition code as soon as possible because if it does not, processing of the branch instructions may be delayed until the condition code is set. Any delay in instruction processing, of course, deleteriously affects the performance of the data processing system.
U.S. Pat. No. 3,881,173 describes a method and apparatus for use in a data processing system wherein the condition code upon which a branch instruction acts is set as a function of the condition-code-setting instruction and a related comparison of the operands of the instruction. The condition code can be calculated before the completion of the execution of the condition-code-setting instruction. The criteria for comparing the operands are determined by the instruction being executed.
In that patent, means are provided within the execution unit for decoding the OP code of an instruction and controlling a comparator within the execution unit for selecting an appropriate comparison criteria for comparing the operands. The operands are concurrently gated into the comparator and a determination is made to set the condition code. The condition code is set within one cycle of the data processing system, or two cycles for double word processing, independently of how many execution cycles are required for a complete execution of the instruction. When a branch instruction interrogates the condition code latch and determines that a branch is to be taken, the branch instruction immediately causes the instruction processing pipeline to be cleared of any instructions in the non-taken instruction stream and commences immediately to process instructions in the to be taken instruction stream.
While the comparison carried out by the method of U.S. Pat. No. 3,881,173 has proved to be very satisfactory, there is still a need for an improved comparator capable of high speed at low cost.